The majority of present day integrated circuits (ICs) are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs), or simply MOS transistors. An MOS transistor includes a gate electrode as a control electrode overlying a semiconductor substrate and spaced-apart source and drain regions in the substrate between which a current can flow. A control voltage applied to the gate electrode controls the flow of current through a channel in the substrate underlying the gate electrode between the source and drain regions. An N-channel MOS (NMOS) transistor utilizes source and drain regions with N-type impurity dopants and a P-channel MOS (PMOS) transistor utilizes source and drain regions with P-type impurity dopants. Complementary MOS (CMOS) devices include a plurality of NMOS transistors and a plurality of PMOS transistors.
MOS transistors, in contrast to bipolar transistor, are majority carrier devices. The gain of an MOS transistor, usually defined by the transconductance (gm), is proportional to the mobility of the majority carrier in the transistor channel. The current-carrying capability and, hence, the performance of an MOS transistor is proportional to the mobility of the majority carrier in the channel. The mobility of holes, the majority carrier in a PMOS transistor, can be increased by applying a compressive longitudinal stress to the channel. Alternatively, to increase the mobility of electrons, the majority carriers in an NMOS transistor, a tensile transverse stress can be applied to the channel of the NMOS transistor.
A tensile transverse stress can be applied to the channel of an NMOS transistor by depositing a tensile stress-inducing material overlying the NMOS transistor and the source and drain regions of the NMOS transistor. Recessed source and drain electrodes can be used to further improve the performance of the NMOS transistors. By recessing the source and drain electrodes, the tensile stress-inducing material can be deposited into the recesses thereby imparting a greater tensile stress into the channel region than if the source and drain electrodes are not recessed.
However, typically the formation of the recesses in a semiconductor substrate is performed with the gate electrode of the NMOS transistor exposed. If the gate electrode is formed of polycrystalline silicon, etching of a silicon substrate, such as by hydrogen bromide (HBr), to from the recesses will result in etching of the exposed polycrystalline silicon electrode. Etching of the polycrystalline silicon electrode reduces the thickness of the electrode. While a mask layer can be used to mask the gate electrode of the NMOS transistor during etching of the recesses, the additional steps to deposit, pattern, and then remove the mask increase the cost of the MOS fabrication and decrease throughput.
Accordingly, it is desirable to provide an improved method for fabricating an NMOS device that minimizes etching of an NMOS polycrystalline silicon gate electrode during etching of recesses into the substrate of the NMOS device. In addition, it is desirable to provide an improved method for fabricating a CMOS device that does not substantially increase the cost of the CMOS device fabrication and decrease throughput. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.